Project Profile

ATSC 3.0 RF Signal Analyzer Performance Test

May 03, 2023

Introduction

The goal of the project was to verify the performance of Avateq's product family of RF signal analyzers and monitoring receivers on a subset of signal formats defined in ATSC A/322 Phy Layer Standard. The subset should include practically reasonable combinations of ModCod and TDM/LDM variants to experimentally verify and confirm AWGN SNR threshold for each PLP included in the test signal.

For the purposes of the test, Gary Sgrignoli, a partner and a technical consultant at Mentel, Sgrignoli and Wallace, LLC (MSW) (https://mswdtv.com/), has created and provided the most relevant signal configurations. The configurations form a list of 10 test signals commonly used by engineers while testing both commercial receivers and professional signal analyzers.

The key objective of the testing procedure was to determine the Avateq's signal analyzer family performance and its degradation caused by possible hardware and DSP imperfections. The obtained experimental results were compared to theoretical limits.

ATSC 3.0 RF Signal Analyzer Performance Test


General Guidelines on Physical Layer Settings

In accordance with ATSC A/327 ATSC Recommended Practice, the certain guidelines in physical layer settings selections which can and should be used in lab testing include:

  • Subframe Pilot Boosting selection (see A/327, 4.2.4) which compromises signal equalization performance with low boosting and appears to be a critical testing scenario for OFDM equalizer performance study.
  • Subframe OFDM configuration including First SBS and Frequency Interleaving allowing for channel imperfections averaging for equalizer enhancement and hence better equalization.
  • Layer Division Multiplexing (LDM) with LDM Injection level as the most advanced way to effectively utilize physical layer resources in diverse reception scenarios both mobile and stationary.
  • ModCod selection targeting signal reception thresholds and LDPC decoding performance.
  • Time interleaver utilization of both inter-frame and intra-frame cells interleaving cases.

Each signal from the test bank targets its unique scenario for both signal equalization technique and LDPC decoder testing and addresses different sources of the potential performance losses in the receiver.


Selection of the Performance Criterion

As the lab testing is usually performed with an observation of the post LDPC Bit Error Rate (BER) for different implementations of SNR (using channel simulator), the key objective of the testing procedure is to derive so called zero errors boundary level which defines the post LDPC BER = 0 over extensive testing period (see A/325, chapter 5).

In accordance with the above statement, the performance was defined as an ability of the AVQx Analyzer to provide correctly de-coded FEC blocks. The criterion is defined as the lowest SNR value at which the output FEC blocks are decoded with post LDPC BER equals 0 over extended time with the required number of LDPC iterations not exceeding 40% of the maximum provided by the DSP chain implementation.


Laboratory Test Setup

The set-up used for the testing included:

All the tests were performed with RF signal power level of -35dBm at 533MHz central frequency.


Results and Summary

The full set of resultant SNR thresholds:

ATSC3 Signal Source InformationAVQ Results
Signal
Name
Virtual
Address
ROUTE
IP
Video
Format
PLP
ID
PLP
Data Rate
PLP
THR1
SNR
THR
(#)(Address)(#)(Mbps)(dB)(dB)
MSW #110.11239.255.4.114K/60PPLP025.8416.5016.1
MSW #210.41239.255.4.41720/30PPLP02.596.306.0
10.12239.255.4.124K/30PPLP117.4916.5016.2
MSW #310.41239.255.4.41720/30PPLP02.556.306.0
10.12239.255.4.124K/30PPLP118.1516.5016.2
MSW #410.41239.255.4.41720/30PPLP02.680.710.5
10.21239.255.4.211080/60PPLP116.2216.7516.4
MSW #510.41239.255.4.41720/30PPLP02.680.710.5
10.21239.255.4.211080/60PPLP113.6416.7516.4
10.42239.255.4.42540/60PPLP21.6011.9512.1
MSW #610.32239.255.4.32720/30PPLP03.540.700.2
MSW #710.42239.255.4.42540/60PPLP01.582.802.5
10.41239.255.4.41720/30PPLP12.537.406.9
10.31239.255.4.31720/60PPLP25.0313.8013.5
10.22239.255.4.221080/30PPLP38.1321.3021.0
MSW #810.42239.255.4.42540/60PPLP01.445.274.9
10.31239.255.4.31720/60PPLP14.9517.1517.0
10.32239.255.4.32720/30PPLP23.867.786.7
10.12239.255.4.124K/30PPLP317.4121.9521.7
MSW #910.42239.255.4.42540/60PPLP01.335.274.9
10.31239.255.4.31720/60PPLP14.5717.1517.0
10.32239.255.4.32720/30PPLP23.747.786.6
10.12239.255.4.124K/30PPLP316.8721.9521.7
MSW #1010.42239.255.4.42540/60PPLP01.295.095.0
10.31239.255.4.31720/60PPLP19.0218.3017.8
10.41239.255.4.41720/30PPLP21.974.524.0
10.22239.255.4.221080/30PPLP39.2218.1518.2

1 - As per Table A.3.2 in A/327:2023-03 ATSC Recommended Practice: Guidelines for the Physical Layer Protocol.

Additionally, it was found that setting a threshold for maximum LDPC iteration to 20 rather than targeting the post LDPC BER = 0 might not only provide a confident estimations of decoder performance but also give a metric of decoding performance degradation with SNR decrease since average number of LDPC iterations over time is a continuous function of the signal SNR values. Such technique, in our opinion, better represents a receiver/demodulator robustness with limited DSP resources.

Such modifications also provide statistical estimations of the average number and deviation of LDPC iterations. Both estimations might be valuable characteristics for further in deep receiver performance degradation study.

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